Semiconductor manufacturing process is typically separated into two major stages: a front-end process stage and a back-end-of-line (hereinafter “BEOL”) process stage. The front-end process refers to the formation of electric devices, such as transistors, and/or electric components, such as resistors and capacitors, on a semiconductor substrate. On the other hand, the BEOL process refers to the formation of metal interconnections between various electric devices and electric components in order to implement a circuitry as designed. Usually, layers of the metal interconnections are insulated by insulating dielectric materials, such as silicon oxide or silicate glass.
Flip chip packaging, also known as controlled collapse chip connection (hereinafter “C4”), is a method for interconnecting semiconductor devices, such as integrated circuit chips and micro-electromechanical systems, to external circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer/substrate during the final BEOL wafer/substrate processing step. To mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect. Note, that this is in contrast to wire bonding, in which the chip is mounted upright and the wires are used to interconnect the chip pads to external circuitry.
Conventional reflow ovens are utilized for chip joining, wherein components of the chip assembly, such as the chip, solder bumps, and laminate substrate, are simultaneously subjected to a temperature in excess of 240° C. for several minutes. Silicon and composite materials included in the laminate substrate have very different coefficients of thermal expansion (hereinafter “CTE”). Thermal expansion refers to the tendency of matter to change in volume in response to a change in temperature. The CTE of a material is the fractional increase in the length per unit rise in temperature. After solder bumps have melted and joined the chip to the substrate they are allowed to cool to room temperature.
However, in doing so, the substrate shrinks more than the chip, which causes the assembly's outermost solder joints to experience shear stress proportional to the difference in the displacements of the silicon and the substrate. When the chips are large enough, the shear stress can deform solder bumps as well as cause the solder to tear from the chip. In the same vein, shear stress can cause the solder joints to crack the chip near its top, which can result in the breaking of wiring layers and/or chip failure. A solution is to use induction heating conducted at an appropriate frequency and time to melt the solder bump while not directly heating either the silicon or the substrate.
Short induction durations are preferable, since some heat will escape from the heated solder bump into both the chip and the substrate by thermal conduction. As the induction duration increases, the amount of heat absorbed by the chip and the substrate increases, which can result in undesirable thermal expansion therein. To address undesirable thermal expansion, shorter induction durations may be performed to create adiabatic conditions, wherein a reduced amount of heat is absorbed by either the chip and/or the substrate. However, as the induction duration decreases, the amount of power required increases, which may increase manufacturing costs.